1. Field of Invention
This invention relates generally to digital logic and specifically to carry-look ahead adders.
2. Description of Related Art
FIG. 1 is a block diagram of a conventional 12-bit carry look-ahead adder 100 having three processing stages in which input signals A[11:0] and B[11:0] are logically combined to generate a 12-bit sum signal S[11:0] and a carry-out bit Cout. In the first stage, groups of three input signal pairs are combined in conventional 3-bit propagate circuits (P3) 200 and 3-bit generate circuits (G3) 300 to produce well-known carry-propagate P[z→x] and carry-generate signals G[z→x], respectively. Specifically, each carry-propagate circuit 200 logically combines three bit-pairings of the input signals A[z:x] and B[z:x] to generate its carry-propagate signal P[z→x] according to the well-known logical expression P[z→x]=(Ax+Bx)|(Ay+Bz)|(Az+Bz), where | denotes the logical AND operation and + denotes the logical OR operation. The groups of three bit-pairings A[z:x] and B[z:x] are also logically combined in G3 circuits 300, each of which generates its carry-generate signal G[z→x] according to the well-known logical expression G[z→x]=Az|Bz+(Az+Bz)|[Ay|By+(Ay+By)|(Ax|Bx)].
In order to maximize speed, P3 circuits 200 and G3 circuits 300 are typically implemented using dynamic logic as shown, for example, in FIGS. 2 and 3, respectively, where PMOS pull-up transistor MP1 and NMOS pull-down transistor MN1 are each responsive to a clock signal CLK. Thus, when CLK is logic low, transistor MP1 turns on and pulls node N1 high to VDD to set the output signal (e.g., P[z→x] or G[z→x]) to logic low via inverter INV1, and transistor MN1 turns off to isolate node N2 from ground potential. When CLK transitions to logic high, transistor MP1 turns off and transistor MN1 turns on, thereby allowing input signals A[z:x] and B[z:x] to determine the logic state of the output signal P[z→x] or G[z→x]. When CLK transitions back to logic low, the output signal is again returned to logic low via inverter INV1 and pull-up transistor MP1.
The second stage of adder 100 includes well-known carry look-ahead (CLA) logic 400 that combines the carry-generate and carry-propagate signals provided by the first stage to simultaneously produce accumulated carry information at 3-bit intervals. Specifically, the carry-generate and carry-propagate signals from respective G3 circuits 300 and P3 circuits 200 are provided to and logically combined in carry look-ahead (CLA) logic 400 to simultaneously produce accumulated carry-generate signals G[2→0], G[5→0], G[8→0], and G[11→0], where G[2→0] represents the carry-out from the first 3 bit positions 0 to 2, G[5→0] represents the carry-out from the first 6 bit positions 0 to 5, G[8→0] represents the carry-out from the first 9 bit positions 0 to 8, and G[11→0] represents the carry-out from all 12 bit positions, and therefore also provides the carry-out bit Cout for adder 100.
CLA logic 400 includes well-known CLA blocks 410, 420, and 430, and in response to the carry-generate G[z→x] and carry-propagate P[z→x] signals, generates in parallel the accumulated carry-generate signals G[2→0], G[5→0], G[8→0], and G[11→0], respectively. G[2→0] is generated by G3 circuit 300a, and may pass unmodified through CLA logic 400. CLA block 410 generates G[5→0] according to the logical expression G[5→0]=G[5→3]+P[5→3]|G[2→0]. CLA block 420 generates G[8→0] according to the logical expression G[8→0]=G[8→6]+P[8→6]|G[5→3]+P[8→6]|P[5→3]|G[2→0]. CLA block 430 generates G[11→0] according to the logical expression G[11→0]=G[11→9]+P[11→9]|G[8→6]+P[11→9]|P[8→6]|G[5→3]+P[11→9]|P[8→6]|P[5→3]|G[2→0]. Exemplary circuit diagrams for CLA blocks 410, 420, and 430 implemented in dynamic logic are shown in FIGS. 4A, 4B, and 4C, respectively.
The third stage of adder 100 includes conventional sum circuits 500 that together logically combine the accumulated carry information provided by the second stage CLA logic 400 with the input signals A[11:0] and B[11:0] to generate the sum signal S[11:0]. Specifically, a grounded signal Cin and the accumulated carry-generate signals G[2→0], G[5→0], and G[8→0] are provided as carry-in signals to respective sum circuits 500a-500d to generate corresponding 3-bit groups of the sum signal in a well-known manner. For example, sum circuit 500a combines A[2:0], B[2:0], and a grounded (i.e., logic low) carry-in bit Cin to generate sum bits S[2:0], sum circuit 500b combines A[5:3], B[5:3], and carry-in bit G[2→0] to generate sum bits S[5:3], sum circuit 500c combines A[8:6], B[8:6], and carry-in bit G[5→3] to generate sum bits S[8:6], and sum circuit 500d combines A[11:9], B[11:9], and carry-in bit G[8→6] to generate sum bits S[11:9].
Typically, each sum circuit 500 generates well-known sum0 and sum1 signals in response to the input signals A and B, and uses the carry-in bit (e.g., G[z→x]) to select between outputting either the sum0 or sum1 bits to form the sum signal S. For example, FIG. 5 shows a conventional 3-bit sum circuit 500 including 3-bit carry-ripple adders. Three sum0 bits are generated by full adders 502a-502c in response to logical combinations of Ax and Bx, Ay and By, and Az and Bz, respectively, with a logic low (i.e., grounded) carry-in bit Cin, and three sum1 bits are generated by full adders 504a-504c in response to logical combinations of Ax and Bx, Ay and By, and Az and Bz, respectively, with a logic high (i.e., tied to VDD) carry-in bit Cin. Multiplexers 506a-506c selectively output either the sum0 or sum1 bits as respective sum bits Sx, Sy, and Sz in response to the logic state of the corresponding carry signal G[u→w]. Because the sum0 and sum1 bits are generated before G[u→w] is available, the 3-bit carry-ripple adders of sum circuit 500 do not degrade performance of adder 100.
Although CLA adder 100 is much faster than carry-ripple adders, it would nevertheless be desirable to further improve its performance. For example, referring again to FIG. 2, P3 circuit 200 includes two paths of three transistors connected in series between nodes N1 and N2 (i.e., transistors 201-203 and transistors 204-206), and thus has a stack height of three. Referring to FIG. 3, G3 circuit 300 includes a discharge path having four stacked input transistors 306-309 connected in series between nodes N1 and N2, and thus has a stack height of four. Because of the well-known body effect phenomenon, the addition of each stacked input transistor significantly reduces the switching speed of the corresponding logic circuit. As a result, because G3 circuit 300 has a stack height of four and P3 circuit 200 has a stack height of three, G3 circuit 300 is much slower than P3 circuit 200, and therefore determines the critical path of the adder 100. Accordingly, it would be desirable to reduce the stack heights of the first stage logic circuits 200 and 300 in order to increase performance.
In addition, G3 circuit 300 includes one discharge path having four stacked input transistors 306-309 and another discharge path having only two stacked input transistors 301-302. Since the series resistance of the four transistors 306-309 is much greater than the series resistance of the two transistors 301-302, transistors 306-309 are typically sized to be much larger than transistors 301-302 in order to maintain similar speeds for their respective discharge paths. However, increasing the size of transistors 306-309 in an effort to achieve balanced operation also increases parasitic capacitances, which in turn further reduces the speed of G3 circuit 300. Increasing the size of transistors 306-309 also increases the input capacitance of circuit 300, which in turn undesirably loads circuitry (not shown) that provides input signals to circuit 300. Thus, it would also be desirable for an adder's first stage logic circuits to have better-balanced discharge paths.